1. Field of the Invention
The present invention is directed to methods of manufacturing integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method of optimizing die yield in a silicon wafer.
2. Description of the Prior Art
In the manufacture of integrated circuit devices, a silicon wafer is typically partitioned into die or dice each having an identical arrangement of semiconductor structures. The die are formed on the silicon wafer by a photolithography tool, called a stepper. The stepper prints the die in groups, called shots, on the surface of the silicon wafer. Photo resist films are deposited and etched on the wafer to expose specific areas of the die to various manufacturing processes. The removal of the buildup of the resist films at the edge of the wafer result in an unusable space on the edge of the wafer called the edge exclusion zone. The number of die formed in the usable area of the silicon wafer that perform satisfactorily to design specifications is called the wafer yield.